1. Field of the Invention
The present invention relates to transmission devices and electronic apparatuses for transmitting data signals and a clock signal, which is used on the reception device side to reproduce the data signals, in one direction to a reception device. More particularly, the present invention relates to a transmission device and an electronic apparatus with a self-diagnostic function for making a diagnosis as to whether the device/apparatus itself is operating normally, and also to a self-diagnostic method for use therein.
2. Description of the Background Art
In recent years, DVI (Digital Visual Interface), HDMI (High Definition Multimedia Interface), and LVDS (Low Voltage Differential Signaling) have been employed as display interface standards. In these standards, the transmission device transmits, to the reception device, data signals and a clock signal in the form of digital signals without any modification. The reception device detects the data signals in accordance with the transmitted clock signal. These standards are used only in one-way communication from the transmission device to the reception device.
FIG. 13 is a block diagram illustrating a general system concept in the case of using the DVI to transmit data from an electronic apparatus 90 on the transmission side to a reception apparatus 93 on the reception side. In FIG. 13, the electronic apparatus 90 includes a data source 91, and a transmission device 92. Parallel digital data outputted from the data source 91 is inputted to the transmission device 92, and converted into serial digital signals Tx0, Tx1, and Tx2. The transmission device 92 transmits the serial digital signals Tx0, Tx1, and Tx2 to a reception device 94, and also transmits to the reception device 94 a clock signal TxC having the same frequency as that of the parallel digital data outputted from the data source 91. The digital signals Tx0, Tx1, and Tx2 and the clock signal TxC are transferred via dedicated cables 96 to the reception device 94. The reception device 94 reproduces the digital data outputted from the data source 91, in accordance with the digital signals Tx0, Tx1, and Tx2 and the clock signal TxC, and transmits the reproduced data to an output unit 95. The output unit 95 outputs, for example, an image based on the digital data from the reception device 94.
FIG. 14 is a block diagram illustrating the functional configuration of the conventional transmission device 92. In FIG. 14, the transmission device 92 includes first through third parallel/serial conversion units 921, 922, and 923, a transmission phase-locked loop circuit (TxPLL) 924, a frequency dividing circuit 925, and a differential output circuit 926.
The TxPLL 924 receives a pixel clock from 25 to 82.5 MHz. The TxPLL 924 decuples the frequency of the pixel clock, and outputs the resultant clock as a clock TxCK. The clock TxCK is inputted to parallel/serial converters (labeled “10to1” in the figure) 921a, 922a, and 923a. Furthermore, the frequency of the clock TxCK is reduced to 1/10 by the frequency dividing circuit 925, and inputted to the differential output circuit 926. The differential output circuit 926 converts the inputted signal into a differential signal, which is outputted as a differential clock signal TxC.
The first through third parallel/serial conversion units 921, 922, and 923 each receive transmission data, which is 10-bit parallel digital data. The frequency of the parallel digital data is the same as that of the pixel clock. The parallel/serial converters 921a, 922a, and 923a are serializers for converting parallel data into serial data. The parallel/serial converters 921a, 922a, and 923a convert the transmission data, which is 10-bit parallel data, into serial data in accordance with the clock TxCK, which is a tenfold clock inputted from the PLL circuit 924, and output the serial data. The serial data outputted from the parallel/serial converters 921a, 922a, and 923a is inputted to differential output circuits 921b, 922b, and 923b, respectively. The differential output circuits 921b, 922b, and 923b convert the inputted serial data into a differential data signal, and output the differential data signals Tx0, Tx1, and Tx2, respectively.
In this manner, the clock signal TxC and the data signals Tx0, Tx1, and Tx2 are outputted from the transmission device 92, and respectively transferred via cables 930, 927, 928, and 929 matched with 50 ohms to the reception device side. Note that the difference in potential between the differential signals is assumed here to be 3.3 V, but it may be higher or lower.
FIG. 15 is a diagram illustrating examples of the data signals Tx0, Tx1, and Tx2 and the clock signal TxC outputted from the transmission device 92. The data signals and the clock signal are differential signals, and therefore they are transferred while being inverted between high (H) and low (L) levels. In the examples shown in FIG. 15, when the data transitions from “1” to “0”, H is inverted to L. As shown in FIG. 15, the data signals Tx0, Tx1, and Tx2 are transferred in synchronization with the clock signal TxC.
As described above, in the DVI standard and suchlike, the data signals and the clock signal are transferred in one direction from the transmission side to the reception side. Note that in the DVI, the data signals Tx0, Tx1, and Tx2 are each assigned an RGB value. Note that the DVI is described in, for example, Japanese Laid-Open Patent Publication No. 2003-218843.
In the above standards, the digital data is transmitted at extremely high speed, and therefore the data cannot be reproduced on the reception side unless the transmission device 92 operates normally. Therefore, it is necessary to diagnose with high accuracy whether the transmission device 92 is normally operating.
Conventionally, in order to diagnose whether the transmission device 92 is operating normally, the following methods have been generally employed. Specifically, a tester (not shown) is provided on the output side of the transmission device 92, and the transmission device 92 is caused to transmit known data, so that the tester can diagnose whether the transmission device 92 is operating normally, based on whether the tester can receive the known data normally. If the data received by the tester is different from the transmitted data, the transmission device 92 can be diagnosed as malfunctioning.
In the above standards, however, the transmission data is transferred at extremely high speed, and therefore the diagnostic tester is also required to operate at high speed. Incorporating functions for allowing the tester to operate at high speed and with high accuracy makes the tester extremely expensive.
Note that as for communication control circuits in conformity with the IEEE 1394 standard, an invention that allows the communication control circuits to make a self-diagnosis without using the tester has been disclosed (see Japanese Laid-Open Patent Publication No. 2001-308883), but no invention has been disclosed regarding self-diagnosis according to the standards, such as DVI, HDMI and LVDS, in which the data signals and the clock signal are transmitted in one direction from the transmission device to the reception device.